{"id":217,"date":"2010-12-30T15:55:00","date_gmt":"2010-12-30T14:55:00","guid":{"rendered":"http:\/\/www.anyma.ch\/blogs\/research\/?p=217"},"modified":"2010-12-30T15:55:00","modified_gmt":"2010-12-30T14:55:00","slug":"sk60-delay-first-steps","status":"publish","type":"post","link":"http:\/\/www.anyma.ch\/blogs\/research\/2010\/12\/30\/sk60-delay-first-steps\/","title":{"rendered":"sk60-delay, first steps"},"content":{"rendered":"<p>On the way home from <a href=\"http:\/\/obsolescence.wikidot.com\/\">Obsolence, Paris<\/a>, Flo and I started to sketch the sk60-delay module.<\/p>\n<p>Ultimately I&#8217;d like an adjustable delay from 1 to around 16 frames &#8211; no way to do this strictly analog, other than using two tape machines, as we did at the <a href=\"http:\/\/www.shiftfestival.ch\">Shift Festival<\/a> or some sort of magnetic drum (but that&#8217;s a project for later&#8230;). For a convenient small module, the only way we see is something around the lines of:<\/p>\n<ol>\n<li>Convert to digital<\/li>\n<li>Stuff into RAM<\/li>\n<li>Read out later<\/li>\n<li>Convert back to analog<\/li>\n<\/ol>\n<p>I was sure I would not get the timings right on the first time, so we designed the following experimental platform around the <a id=\"ctl00_ContentMain_CartGrid_grid_ctl04_ctl00_lnkManufacturerPartNumber\" href=\"https:\/\/ch.mouser.com\/Search\/ProductDetail.aspx?R=TLC5510INSvirtualkey59500000virtualkey595-TLC5510INS\">TLC5510INS<\/a> 20Msps ADC, Cypress <a id=\"ctl00_ContentMain_CartGrid_grid_ctl07_ctl00_lnkManufacturerPartNumber\" href=\"https:\/\/ch.mouser.com\/Search\/ProductDetail.aspx?R=CY62158ELL-45ZSXIvirtualkey63930000virtualkey727-CY62158ELL45ZSXI\">CY62158ELL-45ZSXI<\/a> 8MBit SRAM and a <a id=\"ctl00_ContentMain_CartGrid_grid_ctl05_ctl00_lnkManufacturerPartNumber\" href=\"https:\/\/ch.mouser.com\/Search\/ProductDetail.aspx?R=TLC7524CNSvirtualkey59500000virtualkey595-TLC7524CNS\">TLC7524CNS<\/a> 10Msps DAC.<\/p>\n<p><a href=\"http:\/\/www.anyma.ch\/blogs\/research\/wp-content\/uploads\/2010\/12\/sk60_delay_test_2010_12_30.zip\">sk60_delay_test_2010_12_30<\/a> &#8211; Eagle schematics and board files.<\/p>\n<p>Some numbers:<\/p>\n<ul>\n<li>10mhz samplingrate gives us 10MB\/s<\/li>\n<li>100ns between samples<\/li>\n<li>1 frame = 1\/25 second ( 40ms )<\/li>\n<li>400KB \/ Frame<\/li>\n<\/ul>\n<p>8MBit SRAM = 1MB, so this gives us only a tenth of a second or 2.5 frames delay per RAM chip. We decided to put the RAM on small modules with individual adressing, to be able to add more RAM.<\/p>\n<p>But that&#8217;s for later, first we&#8217;d have to test the concept. The parts arrived from Mouser some days ago, so with Max we decided to give it a first try.<\/p>\n<p><a href=\"http:\/\/www.anyma.ch\/blogs\/research\/wp-content\/uploads\/2010\/12\/DSC05970.jpg\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-219\" title=\"DSC05970\" src=\"http:\/\/www.anyma.ch\/blogs\/research\/wp-content\/uploads\/2010\/12\/DSC05970.jpg\" alt=\"\" width=\"320\" height=\"240\" srcset=\"http:\/\/www.anyma.ch\/blogs\/research\/wp-content\/uploads\/2010\/12\/DSC05970.jpg 320w, http:\/\/www.anyma.ch\/blogs\/research\/wp-content\/uploads\/2010\/12\/DSC05970-300x225.jpg 300w\" sizes=\"(max-width: 320px) 100vw, 320px\" \/><\/a><a href=\"http:\/\/www.anyma.ch\/blogs\/research\/wp-content\/uploads\/2010\/12\/DSC05973.jpg\"><img loading=\"lazy\" decoding=\"async\" class=\"alignleft size-full wp-image-220\" title=\"DSC05973\" src=\"http:\/\/www.anyma.ch\/blogs\/research\/wp-content\/uploads\/2010\/12\/DSC05973.jpg\" alt=\"\" width=\"320\" height=\"240\" srcset=\"http:\/\/www.anyma.ch\/blogs\/research\/wp-content\/uploads\/2010\/12\/DSC05973.jpg 320w, http:\/\/www.anyma.ch\/blogs\/research\/wp-content\/uploads\/2010\/12\/DSC05973-300x225.jpg 300w\" sizes=\"(max-width: 320px) 100vw, 320px\" \/><\/a><\/p>\n<h3>Timing sequence<\/h3>\n<ol>\n<li>Increment RAM address<\/li>\n<li>Read RAM (is automatically triggered by address change if !RAM_WE is high)<\/li>\n<li>Convert to digital (ADC must be in high impedance)<\/li>\n<li>Latch DAC<\/li>\n<li>Enable outputs of ADC<\/li>\n<li>Write RAM<\/li>\n<\/ol>\n<p>Initially I wanted to trigger the different steps with a decade counter and a much faster clock, but by mistake I drew a 4040 binary counter into the schematic. This doesn&#8217;t help much. So we decided to try to hook everything to the same clock and see what happens.<\/p>\n<p>I glued a hex inverter onto the board and tried the following:<\/p>\n<p>PLL clock goes to ADC_CLK, RAM_COUNTER, !DAC_WR<br \/>\nInverted clock to RAM_WE, ADC_OE<\/p>\n<p>after some fiddling with the usual errors we actually had a delayed video signal!<\/p>\n<h3>Observations<\/h3>\n<ul>\n<li>The PLL <a id=\"ctl00_ContentMain_CartGrid_grid_ctl03_ctl00_lnkManufacturerPartNumber\" href=\"https:\/\/ch.mouser.com\/Search\/ProductDetail.aspx?R=CD4046BNSRvirtualkey59500000virtualkey595-CD4046BNSR\">CD4046BNSR<\/a> that we wanted to use as a CV-adjustable clock doesn&#8217;t go up to 10Mhz (only 0.8 at 5V). No colors, obviously, at &lt;1Mhz. The PLL seems not stable enough anyway: vertical lines got quite distorted.<\/li>\n<li>There&#8217;s some &#8220;residue&#8221; of the original image coming through. Maybe the DAC sees some data from the ADC directly? Would be a timing issue.<\/li>\n<\/ul>\n<p>We found a 10Mhz crystal lying around and used a spare inverter to drive it.<\/p>\n<ul>\n<li>At 10Mhz colors come through and there seems to be no phase shift. Quite surprising.<\/li>\n<li>But the delay is completely gone.<\/li>\n<\/ul>\n<p>Devided the clock by 2.<\/p>\n<ul>\n<li>At 5Mhz colors are almost gone (not very surprising)<\/li>\n<li>The delay works again, but there&#8217;s even more &#8220;residue&#8221; of the un-delayed image.<\/li>\n<\/ul>\n<p>I really think the ADC doesn&#8217;t shut of its outputs fast enough &#8211; I&#8217;ll try to build a small delay line with hex inverters to trigger things in the right order&#8230;<\/p>\n","protected":false},"excerpt":{"rendered":"<p>On the way home from Obsolence, Paris, Flo and I started to sketch the sk60-delay module. Ultimately I&#8217;d like an adjustable delay from 1 to around 16 frames &#8211; no way to do this strictly analog, other than using two tape machines, as we did at the Shift Festival or some sort of magnetic drum [&hellip;]<\/p>\n","protected":false},"author":2,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[7],"tags":[],"_links":{"self":[{"href":"http:\/\/www.anyma.ch\/blogs\/research\/wp-json\/wp\/v2\/posts\/217"}],"collection":[{"href":"http:\/\/www.anyma.ch\/blogs\/research\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"http:\/\/www.anyma.ch\/blogs\/research\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"http:\/\/www.anyma.ch\/blogs\/research\/wp-json\/wp\/v2\/users\/2"}],"replies":[{"embeddable":true,"href":"http:\/\/www.anyma.ch\/blogs\/research\/wp-json\/wp\/v2\/comments?post=217"}],"version-history":[{"count":2,"href":"http:\/\/www.anyma.ch\/blogs\/research\/wp-json\/wp\/v2\/posts\/217\/revisions"}],"predecessor-version":[{"id":222,"href":"http:\/\/www.anyma.ch\/blogs\/research\/wp-json\/wp\/v2\/posts\/217\/revisions\/222"}],"wp:attachment":[{"href":"http:\/\/www.anyma.ch\/blogs\/research\/wp-json\/wp\/v2\/media?parent=217"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"http:\/\/www.anyma.ch\/blogs\/research\/wp-json\/wp\/v2\/categories?post=217"},{"taxonomy":"post_tag","embeddable":true,"href":"http:\/\/www.anyma.ch\/blogs\/research\/wp-json\/wp\/v2\/tags?post=217"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}