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sk60-delay, first steps
Categories: Synkie

On the way home from Obsolence, Paris, Flo and I started to sketch the sk60-delay module.

Ultimately I’d like an adjustable delay from 1 to around 16 frames – no way to do this strictly analog, other than using two tape machines, as we did at the Shift Festival or some sort of magnetic drum (but that’s a project for later…). For a convenient small module, the only way we see is something around the lines of:

  1. Convert to digital
  2. Stuff into RAM
  3. Read out later
  4. Convert back to analog

I was sure I would not get the timings right on the first time, so we designed the following experimental platform around the TLC5510INS 20Msps ADC, Cypress CY62158ELL-45ZSXI 8MBit SRAM and a TLC7524CNS 10Msps DAC.

sk60_delay_test_2010_12_30 – Eagle schematics and board files.

Some numbers:

  • 10mhz samplingrate gives us 10MB/s
  • 100ns between samples
  • 1 frame = 1/25 second ( 40ms )
  • 400KB / Frame

8MBit SRAM = 1MB, so this gives us only a tenth of a second or 2.5 frames delay per RAM chip. We decided to put the RAM on small modules with individual adressing, to be able to add more RAM.

But that’s for later, first we’d have to test the concept. The parts arrived from Mouser some days ago, so with Max we decided to give it a first try.

Timing sequence

  1. Increment RAM address
  2. Read RAM (is automatically triggered by address change if !RAM_WE is high)
  3. Convert to digital (ADC must be in high impedance)
  4. Latch DAC
  5. Enable outputs of ADC
  6. Write RAM

Initially I wanted to trigger the different steps with a decade counter and a much faster clock, but by mistake I drew a 4040 binary counter into the schematic. This doesn’t help much. So we decided to try to hook everything to the same clock and see what happens.

I glued a hex inverter onto the board and tried the following:

Inverted clock to RAM_WE, ADC_OE

after some fiddling with the usual errors we actually had a delayed video signal!


  • The PLL CD4046BNSR that we wanted to use as a CV-adjustable clock doesn’t go up to 10Mhz (only 0.8 at 5V). No colors, obviously, at <1Mhz. The PLL seems not stable enough anyway: vertical lines got quite distorted.
  • There’s some “residue” of the original image coming through. Maybe the DAC sees some data from the ADC directly? Would be a timing issue.

We found a 10Mhz crystal lying around and used a spare inverter to drive it.

  • At 10Mhz colors come through and there seems to be no phase shift. Quite surprising.
  • But the delay is completely gone.

Devided the clock by 2.

  • At 5Mhz colors are almost gone (not very surprising)
  • The delay works again, but there’s even more “residue” of the un-delayed image.

I really think the ADC doesn’t shut of its outputs fast enough – I’ll try to build a small delay line with hex inverters to trigger things in the right order…

3 Comments to “sk60-delay, first steps”

  1. flo says:

    74HC für alle cmos chips.
    dann unbedingt anti-aliasing filter.
    einfacher lowpass 5 Mhz am eingang
    und das selbe am ausgang.sollte dann schon deftig helfen.
    oder noch besser am ausgang mit einem der opamps ein 2pole butterworth filter.
    c1=2 x c2, r1=r2= 0.707/(2 x PI x Fo x C2)
    c1=2 x c2=20pf -> c2=10pf ,r1=r2=2250 ohm
    c1=2 x c2=44pf-> c2=22pF ,r1=r2=1022 ohm

  2. chris says:

    amazing work guys love the project

    have you seen this video synth forum ?
    I’m sure they would appreciate your input

    see ya.

  3. max says:

    Zum adressieren: ev. ein 1-aus-N Zähler mit N synchronen 4-bit Binär Zählern (z. B. 74AS163) ? Müsst dann ein konstantes delay geben für clock -> neue addresse.

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